The overcast fall day of October 9, 2012 brought Shep and I to the University of Massachusetts Amherst to co-present a talk about Operationalizing Platforms at Atomic Rules. Dr. Russell Tessier hosted and introduced us to many of his students and colleagues. This brought opportunities to learn of current research projects in his group, the sharing of ideas and in general lots of good collaboration with others in the FPGA community.
Title: Enabling Open-Source FPGA Platforms in a World of Complex Concurrency
Abstract: The advance of Moore’s law is driving a continuous evolution of silicon where the canvas on which the digital designer can create value is everwidening. A productivity gap exists where the design and verification of IP cannot keep pace with Moore’s law. The effects of this gap are evident not just at the gate level, but at the board or platform level, where wide I/O diversity and concurrency throw additional heterogeneity into the mix.
In this informal talk we will explain how Atomic Rules tackles the problems of composing IPs into solutions across multiple platforms. We will describe the situation of weak interface semantics and implicit assumptions that stand in the way of component-based design and how this situation might be improved. We will specifically discuss our experiences with platforms including the Ettus N210, Xilinx KC705 and Altera Stratix.
Looking forward in our week, there is a need to push onward with current projects. We are eagerly anticipating Vivado's update next week as well as a many opportunities to achieve BSV greatness.
UMass Amherst Presentation
Thursday, September 20, 2012
ChipScope has been a useful tool for debugging implemented designs on Xilinx FPGAs. Xilinx's new design suite, Vivado, simplifies the process of adding Integrated Logic Analyzer (ILA) cores for debugging with Vivado Logic Analyzer. No need to hook up cores and wires or launch the old-fashioned ChipScope Inserter and Analyzer, it's all done for you yielding a quick and painless debugging process. Logic analysis is built into Vivado's PlanAhead-like GUI using the same familiar waveform viewer as ISim. Simply launch the Debug Set Up wizard to select signals to monitor, re-synthesize and apply trigger conditions. Clock domains are resolved automatically when nets are selected for debugging, as seen below. I am thankful for this great tool from Xilinx which allows us to be that much more productive and awesome.
Wednesday, September 5, 2012
The first few weeks here at Atomic Rules have surpassed all expectation. BSV lecture slides, tutorials, user guides and reference manuals have dominated week two. I have successfully gone from BSV to bitstream twice last week on my Xilinx KC705 with two "Hello World" bitstreams. The first was a simple blinking LED project (LED705) which assigned the 8 MSBs of a 32 bit binary counter to the 8 on board LEDs resulting in a nice pattern of LED blinks. The second extended LED705 to include displaying characters on the LCD screen. See the photograph below. Forging on to bigger and better BSV projects!
Shell and I are getting settled here in New England which is quite the change for us. We love the gorgeous landscape and are looking forward to the vibrant colors of fall. Shell and I at Livingston Park in Manchester, NH.
Thursday, August 23, 2012
Christina Smith here. I am a Masters student at the University of Arkansas studying Computer Engineering. Currently, I am Shep Siegel’s intern at Atomic Rules as an Assistant Engineer. A six day journey brought me to Auburn, New Hampshire on Saturday for the fall semester. My sweet pup Shell traveled with me as my copilot and road tripping best friend.
My time at Atomic Rules began Monday, August 20 with an eager welcome from Shep. Great strides have been made in my first few days which I am pleased with. A myriad of platforms (Ettus N210, Xilinx KC705 and ML605) have me excited and eager to design some circuits via BDW and BSV. But first comes a few weeks of getting my feet under me and getting settled in.